revision 1.0 apr. 2004 1 r0201-BS616LV1016 very low power/voltage cmos sram 64k x 16 bit ? vcc operation voltage : 4.5v ~ 5.5v ? very low power consumption : vcc = 5.0v c-grade : 48ma (55ns) operating current i- grade : 50ma (55ns) operating current c-grade : 36ma (70ns) operating current i- grade : 38ma (70ns) operating current 1.3ua (typ.) cmos standby current ? high speed access time : -55 55ns -70 70ns ? automatic power down when chip is deselected ? three state outputs and ttl compatible ? fully static operation ? data retention supply voltage as low as 1.5v ? easy expansion with ce and oe options ? i/o configuration x8/x16 selectable by lb and ub pin the BS616LV1016 is a high performance, very low power cmos static random access memory organized as 65,536 words by 16 bits and operates from a range of 4.5v to 5.5v supply voltage. advanced cmos technology and circuit techniques provide both high speed and low power features with a typical cmos standby current of 1.3ua at 5v/25 o c and maximum access time of 55ns at 5v/85 o c. easy memory expansion is provided by an active low chip enable(ce) and active low output enable(oe) and three-state output drivers. the BS616LV1016 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. the BS616LV1016 is available in the jedec standard 44-pin tsop type ii and 48-pin bga package. ? description ? features row decoder memory array 512 x 2048 column i/o write driver sense amp column decoder data buffer output a3 a2 a1 data buffer input control gnd vcc oe we ce dq15 dq0 a5 a6 a7 a15 a13 16 16 16 16 14 128 2048 ? block diagram 512 18 a14 a12 a9 a4 a0 a11 a8 address input buffer a10 address input buffer . . . . ub . . . . lb ? product family ? pin configurations brilliance semiconductor, inc . reserves the right to modify document contents without notice. BS616LV1016 g h f e d c b a 12345 a9 a8 nc io15 nc a12 nc a11 a10 a13 we io7 io14 vcc vss io9 io13 a14 io12 io11 io10 nc nc a5 io8 lb ub oe a3 a0 a15 io5 nc a7 a6 io4 io3 io1 io6 vss vcc io2 a4 a1 ce a2 io0 nc 6 a4 a3 a2 a1 a0 ce dq0 dq1 dq2 dq3 vcc gnd dq4 dq5 dq6 dq7 we a15 a14 a13 a12 nc a5 a6 a7 oe ub lb dq15 dq14 dq13 dq12 gnd vcc dq11 dq10 dq9 dq8 nc a8 a9 a10 a11 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 BS616LV1016ec BS616LV1016ei bsi power dissipation speed (ns) standby (i ccsb1 , max) operating (i cc , max) product family operating temperature vcc range 55ns:4.5~5.5v 70ns:4.5~5.5v vcc=5.0v vcc=5.0v 55ns vcc=5.0v 70ns pkg type BS616LV1016ec tsop2-44 BS616LV1016ac +0 o c to +70 o c 4.5v ~ 5.5v 55/70 4ua 48ma 36ma bga-48-0608 BS616LV1016ei tsop2-44 BS616LV1016ai -40 o c to +85 o c 4.5v ~ 5.5v 55/70 8ua 50ma 38ma bga-48-0608
revision 1.0 apr. 2004 2 r0201-BS616LV1016 name function a0-a15 address input these 16 address inputs select one of the 65,536 x 16-bit words in the ram. ce chip enable input ce is active low. chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. the dq pins will be in the high impedance state when the device is deselected. we write enable input the write enable input is active low and controls read and write operations. with the chip selected, when we is high and oe is low, output data will be present on the dq pins; when we is low, the data present on the dq pins will be written into the selected memory location. oe output enable input the output enable input is active low. if the output enable is active while the chip is selected and the write enable is inactive, data will be present on the dq pins and they will be enabled. the dq pins will be in the high impedance state when oe is inactive. lb and ub data byte control input lower byte and upper byte data input/output control pins. dq0 - dq15 data input/output ports these 16 bi-directional ports are used to read data from or write data into the ram. vcc power supply gnd ground ? truth table ? pin descriptions bsi BS616LV1016 mode ce we oe lb ub dq0~dq7 dq8~dq15 vcc current not selected (power down) h x x x x high z high z i ccsb , i ccsb1 output disabled l h h x x high z high z i cc l l dout dout i cc h l high z dout i cc read l h l l h dout high z i cc ll din din i cc hl x din i cc write l l x lh din x i cc
revision 1.0 apr. 2004 3 r0201-BS616LV1016 symbol parameter test conditions min. typ. (1) max. units v dr vcc for data retention ce R vcc - 0.2v v in R vcc - 0.2v or v in Q 0.2v 1.5 -- -- v i ccdr (3) data retention current ce R vcc - 0.2v v in R vcc - 0.2v or v in Q 0.2v -- 0.15 0.8 ua t cdr chip deselect to data retention time 0 -- -- ns t r operation recovery time see retention waveform t rc (2) -- -- ns symbol parameter conditions max. unit c in input capacitance v in =0v 6 pf c dq input/output capacitance v i/o =0v 8 pf range ambient temperature vcc commercial 0 o c to +70 o c 4.5v ~ 5.5v industrial -40 o c to +85 o c 4.5v ~ 5.5v ? data retention characteristics ( ta = -40 o c to + 85 o c ) ? absolute maximum ratings (1) ? operating range ? capacitance (1) (ta = 25 o c, f = 1.0 mhz) 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. this parameter is guaranteed and not 100% tested. ? dc electrical characteristics ( ta = -40 o c to + 85 o c ) bsi BS616LV1016 parameter name parameter test conditions min. typ. (1) max. units v il guaranteed input low voltage (2) vcc=5.0v -0.5 -- 0.8 v v ih guaranteed input high voltage (3) vcc=5.0v 2.2 -- vcc+0.3 v i il input leakage current vcc = max, v in = 0v to vcc -- -- 1 ua i lo output leakage current vcc = max, ce = v ih , or oe = v ih , v i/o = 0v to vcc -- -- 1 ua v ol output low voltage vcc = max, i ol = 2ma vcc=5.0v -- -- 0.4 v v oh output high voltage vcc = min, i oh = -1ma vcc=5.0v 2.4 -- -- v 55ns 50 i cc (6) operating power supply current ce = v il , i dq = 0ma, f = fmax (4) 70ns vcc=5.0v -- -- 38 ma i ccsb standby current-ttl ce = v ih , i dq = 0ma vcc=5.0v -- -- 2 ma i ccsb1 (5) standby current-cmos ce R vcc-0.2v, v in R vcc - 0.2v or v in Q 0.2v vcc=5.0v -- 1.3 8 ua symbol parameter rating units v term terminal voltage with respect to gnd -0.5 to vcc+0.5 v t bias temperature under bias -40 to +85 o c t stg storage temperature -60 to +150 o c p t power dissipation 1.0 w i out dc output current 20 ma v cc power supply voltage v -0.5 to vcc+0.5 1. typical characteristics are at ta = 25 o c. 2. undershoot : -1.5v in case of pulse width Q 20ns. 3. overshoot : vcc+1.5v in case of pulse width Q 20ns. 4. fmax = 1/t rc . 5. i cc s b1_max. is 4ua at vcc=5.0v and t a =70 o c. 6. i cc _max. is 48ma(@55ns) / 36ma(@70ns) at vcc=5.0v and ta=0~70 o c. 1. vcc = 1.5v, t a = + 25 o c2.t rc = read cycle time 3. i cc dr_max. is 0.45ua at t a =70 o c.
revision 1.0 apr. 2004 4 r0201-BS616LV1016 input pulse levels vcc/0v input rise and fall times 1v/ns input and output timing reference level 0.5vcc output load c l =30pf+1ttl c l =100pf+1ttl ? ac test conditions (test load and input/output reference) ? key to switching waveforms waveform inputs outputs must be steady may change from h to l don t care: any change permitted does not apply must be steady will be change from h to l change : state unknown center line is high impedance ?off ?state may change from l to h will be change from l to h , ? low v cc data retention waveform ( ce controlled ) ce data retention mode vcc t cdr vcc t r v ih v ih vcc v dr 1.5v ce vcc - 0.2v bsi BS616LV1016 ? ac electrical characteristics ( ta = -40 o c to + 85 o c ) read cycle jedec parameter name parameter name description cycle time : 55ns (vcc = 4.5~5.5v) (vcc = 4.5~5.5v) unit t avax t rc read cycle time 55 -- -- 70 -- -- ns t avqv t aa address access time -- -- 55 -- -- 70 ns t elqv t acs chip select access time -- -- 55 -- -- 70 ns t ba t ba data byte control access time (lb,ub)----25----35 ns t glqv t oe output enable to output valid -- -- 25 -- -- 35 ns t e1lqx t clz chip select to output low z 10 -- -- 10 -- -- ns t be t be data byte control to output low z (lb,ub) 10 -- -- 10 -- -- ns t glqx t olz output enable to output in low z 5 -- -- 5 -- -- ns t ehqz t chz chip deselect to output in high z -- -- 20 -- -- 25 ns t bdo t bdo data byte control to output high z (lb,ub)----20----25 ns t ghqz t ohz output disable to output in high z -- -- 20 -- -- 25 ns t axox t oh data hold from address change 10 -- -- 10 -- -- ns (1) note : min. typ. max. min. typ. max. 1. t ba is 25ns/35ns (@speed=55ns/70ns) with address toggle. ; t ba is 55ns/70ns (@speed=55ns/70ns) without address toggle. cycle time : 70ns
revision 1.0 apr. 2004 5 r0201-BS616LV1016 bsi BS616LV1016 ? switching waveforms (read cycle) read cycle1 (1,2,4) t rc t oh t aa d out address t oh t oh read cycle3 (1,4) t rc t oe d out lb,ub ce oe address t clz t acs t chz (1,5) t ohz t olz t aa read cycle2 (1,3,4) t clz t chz d out lb,ub ce t ba t acs notes: 1. we is high for read cycle. 2. device is continuously selected when ce = v il . 3. address valid prior to or coincident with ce transition low. 4. oe = v il . 5. the parameter is guaranteed but not 100% tested. t be t bdo t bdo t ba t be (5) (5) (5) (5)
revision 1.0 apr. 2004 6 r0201-BS616LV1016 bsi BS616LV1016 t wr ? switching waveforms (write cycle) write cycle1 (1) t wc (3) t cw (10) t bw (2) t wp t aw t ohz (4,11) t as (3) t dh t dw d in d out we lb,ub ce oe address (5) ? ac electrical characteristics ( ta = -40 o c to + 85 o c ) write cycle jedec parameter name parameter name description cycle time : 55ns (vcc = 4.5~5.5v) (vcc = 4.5~5.5v) unit t avax t wc write cycle time 55 -- -- 70 -- -- ns t e1lwh t cw chip select to end of write 55 -- -- 70 -- -- ns t avwl t as address setup time 0---- 0 -- -- ns t avwh t aw address valid to end of write 55 -- -- 70 -- -- ns t wlwh t wp write pulse width 35 -- -- 45 -- -- ns t whax t wr write recovery time (ce,we) 0 -- -- 0 -- -- ns t bw t bw date byte control to end of write (lb,ub)35----45---- ns t wlqz t whz write to output in high z -- -- 25 -- -- 30 ns t dvwh t dw data to write time overlap 35 -- -- 40 -- -- ns t whdx t dh data hold from write time 0 -- -- 0 -- -- ns t ghqz t ohz output disable to output in high z -- -- 20 -- -- 25 ns t whox t ow end of write to output active 5 -- -- 5 -- -- ns 1. t bw is 35ns/45ns (@speed=55ns/70ns) with address toggle. ; t bw is 55ns/70ns (@speed=55ns/70ns) without address toggle. (1) note : min. typ. max. min. typ. max. cycle time : 70ns
revision 1.0 apr. 2004 7 r0201-BS616LV1016 write cycle2 (1,6) bsi BS616LV1016 notes: 1. we must be high during address transitions. 2. the internal write time of the memory is defined by the overlap of ce and we low. all signals must be active to initiate a write and any one signal can terminate a write by going inactive. the data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. t wr is measured from the earlier of ce or we going high at the end of write cycle. 4. during this period, dq pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. if the ce low transition occurs simultaneously with the we low transitions or after the we transition, output remain in a high impedance state. 6. oe is continuously low (oe = v il ). 7. d out is the same phase of write data of this write cycle. 8. d out is the read data of next address. 9. if ce goes low during this period, dq pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 10. t cw is measured from the later of ce going low to the end of write. 11. the parameter is guaranteed but not 100% tested. t wc t cw (10) (2) t wp t aw t whz (4,11) t as t wr (3) t dh t dw d in d out we ce address (5) t ow (7) (8) (8,9) t bw lb,ub
revision 1.0 apr. 2004 8 r0201-BS616LV1016 ? ordering information bsi BS616LV1016 ? package dimensions tsop2-44 note: bsi (brilliance semiconductor inc.) assumes no responsibility for the application or use of any product or circuit described he rein. bsi does not authorize its products for use as critical components in any application in which the failure of the bsi product may be expected to result in signif icant injury or death, including life-support systems and critical medical instruments. BS616LV1016 x x z y y grade c: +0 o c ~ +70 o c i: -40 o c ~ +85 o c speed 55: 55ns 70: 70ns pkg material -: normal g: green p: pb free package e: tsop2-44 a: bga-48-0608
revision 1.0 apr. 2004 9 r0201-BS616LV1016 bsi BS616LV1016 ? package dimensions (continued) 48 mini-bga (6 x 8) d1 view a 1.4 max. e e1 1: controlling dimensions are in millimeters. 2: pin#1 dot marking by laser or pad print. 3: symbol "n" is the number of solder balls. ball pitch e = 0.75 d 8.0 6.0 en 48 3.75 e1 d1 5.25 notes:
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